Stu2 - W7IY

A 6x4 Antenna Switching System

Stu Michell, W7IY
October 4, 2006


The SixPak from WX0B works great for two radios, but the W4RM contest station plans to run with 3 or 4 stations. We needed a way to combine two SixPaks into one, which would provide a 6 by 4 matrix and keep the lock-out function of the SixPak.

This design uses a complex programmable logic device (CPLD) to combine two SixPaks into a single, 6 by 4 matrix. Logic in the control box ensures only one of four radios can connect to a given antenna at a time.

Starting with the SixPak

In the SixPak, there are two relays - one for each band. Selecting one relay locks out the other, so only one of the two radios can select a given antenna. For example, if radio A selects the 160M antenna, Radio B can NOT select the 160M antenna.

Each relay has three DPST contacts. Each band has two relays, A and B. Two contacts are used for the RF path (providing the isolation) and the third contact is in series with the coil of the other relay. So the third contact on relay A is in series with the coil of relay B. Engergizing relay A opens the coil circui of relay B, effectively locking out relay B.

The relays are controlled by a remote switch box, which provides 12Vdc to the desired relay. Each control box has two switches and two rows of cooresponding LEDS. In this project, the right hand switch (Radio B) is disabled and the red LEDs provide feedback from the switch matrix. The green LEDs are switched by the control box.

Design Overview

A complex programmable logic device (CPLD) accepts 24 inputs (6 for each radio) and controls 24 output relays. The output relays provide the required 12VDC to the desired SixPak switch. Output relays isolate the CPLD control circuitry from the long, rotor cable control lines, which run from the house to the tower. Hopefully, this will reduce the chance a near-by lightning strike will damage the CPLD.


Select an antenna using the left switch on the control box. A green LED will light, which indicates the selection. (e.g. 160M) The red LEDs indicate which antennas have been selected.

Once an antenna is selected, the cooresponding red LED will light on all control boxes. If another operator tries to select that antenna, it will not be switched. That is, once an operator selects an antenna, the antenna is removed from the 'pool' and won't be available until the operator switches to another antenna.

Antennas are 'first come, first served.' If an antenna is selected by two operators, the operator who gets there first, wins. If both operators keep the same antenna selected, the second operator picks up the antenna when the first operator switches to another antenna.


A combination of resisters and LEDs reduce the ~12VDC input signal orgininating from the SixPak control box to 2.8 volts The 2.8V signal is applied to the CPLD input pin via a header mounted on the CPLD demo board.


Each CPLD output (24) switches a NPN transistor, which drives a 12VDC relay. The 12VDC relay, in turn, provides 12VDC to the proper control line. Separate supplies provide power to the CPLD and the output control lines. Three relay modules, with 8 relays and LEDs, were cut from a larger control circuit board, which we found at the Manassas Hamfest.

A NPN/PNP transistor combination provides a 12V signal, which is fed back to the SixPak control boxes. The signal lights a red LED, indicating the cooresponding antenna is selected. This lets the operator know an anteanna has been selected by another operator. All four control boxes are fed in parallel.


The high level design links together six switch modules and a reset module. Each switch module ensures only one radio can select a given antenna and the reset module provides a 'power on' reset pulse, which initalizes the switch modules.

Each module has four inputs and four outputs. The input signals connect to input a two-input NAND gate. The other input of the NAND gate connects to a parallel shift register. A logic '1' is shifted through the shift register, which sequencially enables the input NAND gates. If an input is high (logic 1), the input NAND gate switches to a low, which disables the shift register clock signal. Since the shift register is 'stuck' in this state, none of the other inputs can select the antenna.

After the input is released, the corresonding output is disabled and the shift register resumes scanning.

The shift register is preloaded with '1000', which provides the scanning. A VHDL module, provides the load and reset pulses to the switch module. It's fascinating that schematics can be combined with VHDL code to produce a final design!

Six modules provide 24 inputs and 24 outputs, which are connected to the CPLD pins in software. The CPLD pins connect to 0.1" headers, located on the side of the demo board.

The reset VHDL module (LoadReg) is a chunk of code, which provides a reset pulse to the switch module. A counter increments for each clock cycle. When the counter reaches a certain value, the output pin toggles state. When the counter reaches another value, the output pin toggles back to the original state and never toggles again. This provides a 'one-shot' pulse, similar to a 555 timer circuit.

I ran into two 'gotchas' worth mentioning. Within the Xilinx schematic capture tool, I connected the input pin of the shift register to a pull-up resister. When the 'load' signal was toggled low, the inputs transfer to the outputs. I believed the shift register was loaded with '1000,' but it wasn't. It was loaded with '0000' and the input NAND gates were never enabled. In the hardware world, a pull-up resister ties a pin high.' However, in the schematic capture tool, it didn't. I needed to tie the pin directly to Vcc!

Another gotcha - the design worked well, for a while, then it started displaying erratic behavior. Output pins were not activiating appropriately. I purposely left out any debouncing circuits because I thought the rotary switches wouldn't display the same problem as a toggle switch. This was wrong. Luckily, schmidt triggers can be activiated on the CPLD input pins in the UCF constraints file. I solved the problem in software. (Fantastic.)

Xilinx provides the ISE webpack integrated design environment for no charge. I tried the Windows version, but settled on the Linux version because my Linux computer has more horsepower. The simulator included in the Linux version worked fine. The screen display wasn't as pretty as the Windows version and I could have benefited from dual monitors at a higher resolution.

I investigated Altera devices. They provide a free IDE, too. However, I settled on the Xilinx devices because I found an inexpensive ($50) demo board. I'll probably commit to this series of chips because I invested so much time in the IDE. I also understand their Spartan line may be able to run an embedded version of Linux, soon.

The Chip

I chose the Coolruner II in the TQ-144 format because I needed 48 I/O pins. I'm sure the I/O pins can be multiplexed to reduce the pin count to 24, but I think it would require additional IC's (e.g. latches.) Moving to the TQ-144 format excluded the use of simple CPLD sockets, which meant I needed some sort of board with the surface mounted device premounted. While searching the Internet, I found a demo board sold by Digilent, which has two CPLDs, I/O headers, a wire-wrap area, power regulator, push buttons and a couple of LEDs. So I ordered kit with the board, book, CD and JTAG programming cable for $50.

There are two drawbacks for using the demo board. First, the size is much larger than it needs to be. Second, if the chip lets the smoke out, the whole board may need to be replaced. Both of these could be overcome by learning how to solder surface mounted components to a PC board.

Control Boxes

The control box has two rotary switches and two rows of LEDs. The rotary switch on the right hand side (B) is disabled. A trace on the inside of the control box is cut, which prevents the 12V from feeding back into the switch matrix output circuitry. The red LEDs are left in circuit and are controlled by the switch matrix. When the operator selects an antenna, the green LED lights and the cooresponding red LED lights.


The input and output connectors are DB-25s mounted on the bottom of the enclosure. The input connectors are female and the output connectors are male. Both input and output pin assignments are the same. The control and relay cables have DB-25s, too. If the box fails, the cables from the control boxes can be directly connect to the relay cables. In the bypass mode, 12VDC applied to the relay cable provides the power to the control boxes.

RF Stuff

Each antenna connects to a PL-259 T connector. Short stubs connect the T connectors to the SixPak relay boxes, which effectively connects the relay boxes in parallel. Since the stubs are physically short, they are relatively invisable at HF frequencies. (This was much debate about this in our circle of friends, but hey, they are all VHF and microwave guys.)


If we bought all the parts brand new, the total cost for the project would have been over $200. Luckily, we had access to WA0DYJ's junk bin and several major Hamfests, which made our cost just under $100. We had to pay for the demo board ($50), case ($15) and relay boards ($15.) We were able to scrounge the power supplies and connectors, which would have cost us another $50 or so.

The project took much more time than I imagined. I spent about 20 hours wiring up the boards and about 40 hours on the design. This didn't include the time learning Xilinix's ISE software or troubleshooting, which was about another 40 hours. Of course, the learning curve provides the highest entertainment value to an engineer.


If I had it to do all over again, I would have done the following:

Things that went well